1. Field of the Invention
This invention relates generally to over-current sensing and protection of electronic circuits, and more specifically to sensing an over-current condition in a transistor of a half-bridge class D power output stage when its PWM gate drive pulse is so narrow that normal over-current sensing is too slow to detect the over-current condition.
2. Description of the Related Art
Many electronic circuits employ power output stages having bipolar or field effect transistors (FETs) in a half-bridge configuration, often referred to as a class D output stage. In a class D topology, the collector or drain of a first transistor is coupled to the supply voltage PVDD, the emitter or source of a second transistor is coupled to ground, and the emitter or source of the first transistor is coupled to the collector or drain of the second transistor and also to a first terminal of an inductor. The second terminal of the inductor is coupled to a load resistance to ground and to a filter capacitor to ground. Hereinafter, the term FET will be used to refer to a transistor, recognizing that the circuits described may also be realized with bipolar transistors. The FET coupled to PVDD shall be referred to herein as the high side FET, and the FET coupled to ground shall be referred to as the low side FET.
By driving the gates of the FETs of a class D output stage with complementary pulse-width-modulated (PWM) signals sometimes referred to as PWM+ and PWM−, one or the other FET is turned on, coupling either PVDD or ground through the very low resistance of that FET to the load through the inductor. The opposite FET is turned off by its complementary gate drive signal. The filtering action of the inductor and capacitor smooth the pulsating current to the load. By varying the pulse width of the gate drive pulses, the resulting voltage applied to the load may be varied.
One type of circuit using this output stage is a switching voltage regulator, which measures the voltage present at the output, compares it to a desired reference voltage, and adjusts, by use of a feedback loop, the duty cycle of the PWM gate drive signal so as to drive the output voltage to the desired value even as load current and PVDD change. Another application for such an output stage is in Class D audio amplifier circuits, which operate in a manner similar to a switching voltage regulator but which cause the output voltage to follow an input AC audio signal rather than a DC reference voltage. Such amplifiers are typically very efficient, since the output FETs are either off or fully on, dissipating little power in either state.
Various methods for sensing excessive current flowing in the “on” FET have been developed, which typically trigger over-current shutdown of the output circuits to prevent damage to the FETs or other portions of the circuitry. The positive current flowing in a FET is typically measured during the time the gate drive pulse turns on the FET. If an over-current condition during the on time is detected, succeeding pulses may be skipped to allow the current to decrease below the over-current threshold. In the context of this document, positive current shall refer to current flowing from PVDD through the high side FET to the output, or flowing from the output to ground through the low side FET. Negative current shall refer to current flowing in the opposite direction through either FET. Known over-current sensing typically occurs during the time of positive current flow.
However, because of the limited speed of sensing and operation of some of these over-current protection circuits, they may operate unreliably or not at all when the gate drive pulse becomes very narrow. An apparatus and method for providing over-current sensing and protection even with very narrow gate drive pulses is therefore desirable, and is an object of the present invention.